Digital Design FE Engineer M/F
Internship Grenoble (Isère) Community management
Job description
General information
Reference
2020-7066
Job level
30 - Graduate Entry Level
Position description
Posting title
Digital Design FE Engineer M/F
Regular/Temporary
Regular
Job description
The Low Power RF team is looking for a digital design engineer to join the digital RF IP team in Grenoble. The team is in charge to provide a set of advanced digital IP compliant with the latest reference standards for wireless communications (Bluetooth Low energy, SigFox, ISM proprietary, …).
The candidate will be responsible, in collaboration with the team, of
- Review and understand the digital RF IP architecture and define the module’s micro architecture.
- Design in RTL ( VERILOG or VHDL), in respect of target criteria such as low power consumption and silicon area.
- Develop and maintain test bench and simulations to validate and debug the design.
- Collaborate with the Architecture and Digital IP Verification teams for a quick analysis and resolution of the issues.
The candidate should be able to understand the constraints for such IP, related to RF, digital signal processing and System on Chip integration
Profile
Good team work and communication.
Digital Design & Simulation (synopsis/cadence tools and spyglass knowledge would be appreciated).
Strong analytical problem solving and attention to details.
Mixed signal (Analog / Digital) processing knowledge would be appreciated.
Position localisation
Job location
Europe, France, Grenoble
Candidate criteria
Education level required
5 - Master degree
Experience level required
2-5 years
Languages
English (2- Business fluent)
Requester
Desired start date
01/10/2020