Member Technical Staff, D2S, HDLEngine
Internship Noida (Gautam Buddha Nagar) Teaching
Job description
“At Siemens we are always challenging ourselves to build a better future. We need the most innovative and diverse Digital Minds to develop tomorrow‘s reality. Find out more about the Digital world of Siemens here: www.siemens.com/careers/digitalminds
We are technology leader in Electronic Design Automation (EDA), providing software and hardware design solutions that enable companies to send better electronic products to market faster and more cost-effectively.
DFT FrontEnd : Managing the hierarchical data model for both RTL and no-RTL flows keeping in mind performance and capacity and all DFT tools in mind. The model is serialized and restored on-demand for various tool requirements. Enhancing the model for changing language standards. We further have a very powerful set of APIs dealing with test insertion which is done on the same model , the test insertion involves connecting two hierarchical nodes optimally by doing fanin/fanout traversals. This model is further written out to ensure that written out RTL [Verilog, VHDL, System Verilog ] is format preserved
Specific knowledge, skills and academic:
Should have good hands on experience working on C,C++. Sound knowledge on data structures and algorithms will be required. Knowledge on SystemVerilog , VHDL , Verilog will be an advantage.
Key Interactions: Internal/External
Person will be responsible for both internal/external interactions mainly through e-mails.
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Early Professional
Job Type: Full-time